Low Cost Security Aware High Level Synthesis Methodology

Owing to massive complexity of modern digital integrated circuits (ICs) disabling complete inhouse development, globalization of the design process establishes itself as an inevitable solution for faster and efficient design. However, globalization incurs importing intellectual property (IP) cores from various third party (3P) vendors, rendering an IP susceptible to hardware threats. To provide trust and security in digital integrated circuits within user constraints, design of a low cost optimized Dual Modular Redundant (DMR), through Trojan secured high level synthesis (HLS) methodology, is crucial. This paper presents exploration of a low cost optimized HLS solution capable of handling hardware Trojan (providing security) that alters computational output. The key contributions of the paper are as: (1) novel low cost security aware HLS approach, (2) novel encoding for representing bacterium in the design space (comprising of candidate datapath resource configuration and vendor allocation information for Trojan secured solution), (3) novel exploration process of an efficient vendor allocation procedure that assists in yielding a low cost Trojan secured schedule. Experimental results indicate significant reduction in the cost of security aware HLS solution (82.4 %) through the proposed approach compared to a recent approach.